Philipp Tomsich
Chief Technologist at RISC-V International
Vienna, Austria
Summary
🤩
Rockstar🎓
Top SchoolPhilipp Tomsich is a seasoned technologist and founder with 15 years of systems, compiler, and silicon-enablement experience, currently serving as Chief Technologist at VRULL in Vienna. He leads ISA extension design, compiler backends, vectorization strategies, and AI software enablement to turn prototype silicon into production platforms, and has shaped over 10 RISC‑V extensions from spec through upstream toolchain support. An upstream-first engineer and core contributor to GCC, LLVM, QEMU, and Linux, he has hands-on contributions to flagship projects like the Spike RISC‑V ISA simulator and GCC's aarch64/RISC‑V targets. Beyond engineering, he plays leadership roles in RISC‑V International (Vice‑Chair of the Technical Steering Committee and Board Treasurer), bridging technical strategy, governance, and ecosystem growth. His background spans high-assurance government systems, embedded production shipping, and compiler internals—a mix that makes him rare in translating formal specifications into shipping toolchains.
15 years of coding experience
20 years of employment as a software developer
Vienna University of Technology
German, English, French
Github Skills (26)
simulation10
c-language10
float3210
bit-manipulation10
simulator10
simulations10
risc-v10
c1110
c1710
compiler-optimization10
arm10
floating-point10
cprogramming-language10
qemu9
decode9
Programming languages (9)
Github contributions (5)
riscv-software-src/riscv-isa-sim
Jan 2023 - Jun 2023
Spike, a RISC-V ISA Simulator
Role in this project:
Back-end Developer & System Architect
Back-end Developer & System ArchitectContributions:6 reviews, 7 PRs, 1 push in 5 months
Contributions summary:Philipp significantly contributed to the RISC-V ISA simulator, focusing on implementing new instruction set extensions, specifically Zicond and Zfa. Their work involved modifying core simulator components, including the ISA parser, instruction definitions, and related header files. They also addressed exception handling and bit pattern issues for floating-point instructions within the Zfa extension. Furthermore, the user updated and regenerated the `encoding.h` file.
risc-visariscvriscv32simulator
gcc-mirror/gcc
Aug 2022 - Nov 2022
Role in this project:Back-end Developer
Back-end DeveloperContributions:6 commits in 3 months
Contributions summary:Philipp primarily contributed to the GCC compiler, focusing on the aarch64 and RISC-V architectures. Their work involved implementing support for new CPUs (Ampere-1, Ampere-1A, and Ampere-1B), improving instruction fusion, and optimizing code generation for bit manipulation instructions. Additionally, the user fixed existing issues and updated core definitions within the compiler. This work indicates a deep understanding of compiler internals and architecture-specific optimizations.
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