Philipp Wagner
Hardware Verification Engineer
Augsburg, Bavaria, Germany
Summary
🤩
Rockstar🎓
Top SchoolPhilipp Wagner is a hardware verification engineer with 15 years of experience building and validating open-source silicon and tooling, currently at IBM and co-maintainer of the cocotb verification framework. He has deep RISC-V expertise from his work on the Ibex CPU core and contributions to OpenTitan, balancing low-level hardware fixes (debug, compressed instruction handling) with infrastructure improvements like commit linting and build automation. A founding director of the FOSSi Foundation, Philipp blends academic rigor—he holds a Dr.-Ing. from TUM—with pragmatic engineering, turning research prototypes into usable open-source solutions. He’s comfortable across hardware, software, and verification stacks, and is known for improving test robustness and developer experience in widely used projects such as cocotb, FuseSoC and edalize.
15 years of coding experience
9 years of employment as a software developer
Dr.-Ing. (PhD), Electrical Engineering and Information Technology, Dr.-Ing. (PhD), Electrical Engineering and Information Technology at Technical University Munich
English, German
Stackoverflow
31reputation
3kreached
3answers
0questions
Github Skills (42)
git10
verilog10
systemverilog10
pytest10
python10
computer-architecture10
architecture10
testing10
risc-v10
verification10
hardware10
eda10
package-manager-tool10
verilator10
sys10
Programming languages (26)
Github contributions (5)
lowRISC/ibex
Jan 2019 - Jul 2021
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Role in this project:
Embedded Systems Engineer / Hardware Engineer
Embedded Systems Engineer / Hardware EngineerContributions:86 reviews, 192 commits, 338 PRs in 2 years 7 months
Contributions summary:Philipp's contributions primarily involve enhancing and improving the Ibex RISC-V CPU core. The user added Doxygen-style module descriptions to improve code documentation, making the code more accessible. They also fixed issues related to the debug implementation and handling of compressed instructions, notably ensuring single-stepping functionality, and supported the MISA CSR. Furthermore, the user made improvements to the tracer and the compliance test framework.
risc-vcpuzeroibex32-bit
cocotb/cocotb
Nov 2017 - Jan 2023
cocotb: Python-based chip (RTL) verification
Role in this project:QA Engineer / Test Automation Engineer
QA Engineer / Test Automation EngineerContributions:17 releases, 310 reviews, 299 commits in 5 years 3 months
Contributions summary:Philipp contributed to the test suite for the cocotb project, focusing on enhancing the robustness and accuracy of the test environment. Their work involved fixing sporadic test failures, implementing tests for new features, and ensuring compatibility with different Python versions and simulators. They demonstrated proficiency in identifying and addressing bugs, improving test coverage, and maintaining the reliability of the verification framework.
uvmpythonvhdlcosimulationcoroutine
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