System Validation Software Engineer CPU & Memory Hierarchy
San Francisco Bay Area United States
Join Prog.AI to see contacts
Join Prog.AI to see contacts
Summary
👤
Senior
🎓
Top School
Phillip Trent is a System Validation Software Engineer with 11 years of hands-on experience focused on CPU and memory hierarchy validation for ARM-based SoCs, currently validating compute-centric Apple Silicon. He specializes in kernel- and pre-/post-silicon validation, bringing together deep hardware understanding and low-level software skills across memory management, virtualization, security, and SoC architecture. His background includes system-level stress and fault-injection work at Xilinx—debugging ARM cores, SMMU, CMN-600, PCIe, and ECC systems—and collaboration with hardware designers to close RTL bugs. Phillip thrives in environments that reward perfectionism and craftsmanship, often building bespoke bare-metal tools and drivers to reproduce elusive hardware faults. Based in the San Francisco Bay Area with a University of Pennsylvania engineering degree and exchange experience at ETH Zürich, he combines academic rigor with practical prototyping experience from startups to hyperscale silicon. A not-obvious strength: he pairs deep technical debugging with cross-disciplinary communication, routinely translating silicon failure modes into actionable RTL and software fixes.
11 years of coding experience
4 years of employment as a software developer
N/A, Computer Engineering, Exchange Student, N/A, Computer Engineering, Exchange Student at ETH Zürich
Bachelor of Science in Engineering (B.S.E.), Computer Engineering, Bachelor of Science in Engineering (B.S.E.), Computer Engineering at University of Pennsylvania
Contributions:2 PRs, 1 push, 1 branch in 2 years 4 months
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.
Request Free Trial
Phillip Trent - System Validation Software Engineer CPU & Memory Hierarchy