Pirmin Vogel
Silicon Lead at lowRISC CIC
Thalwil, Zurich, Switzerland
Summary
🤩
Rockstar🎓
Top SchoolPirmin Vogel is a Silicon Lead with 11 years of hands-on experience in digital design, hardware security and system-level integration, primarily focused on open-source silicon like OpenTitan. He combines ASIC/FPGA design and verification with low-level kernel and user-space software expertise, and has driven fault-injection and side-channel countermeasures across AES, KMAC/SHA3 and OTBN. As co-tapeout lead and builder of the Zurich design/security team, he blends technical leadership with practical project delivery and academic collaboration (ETH Zürich). He is also an active contributor to lowRISC projects such as the Ibex RISC‑V core, where he improved maintainability and instruction support—demonstrating a rare mix of formal verification, hardware-software co-design and production silicon experience.
11 years of coding experience
5 years of employment as a software developer
Doctor of Philosophy - PhD Electrical Engineering and Information Technology, Doctor of Philosophy - PhD Electrical Engineering and Information Technology at ETH Zürich
English, German, French
Github Skills (10)
risc-v10
embedded10
assembly10
systemverilog10
bit-manipulation10
sys10
assembler10
digital-design9
hardware-designs9
verilog9
Programming languages (11)
Github contributions (5)
lowRISC/ibex
May 2019 - Jan 2023
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Role in this project:
Back-end Developer & Embedded Systems Engineer
Back-end Developer & Embedded Systems EngineerContributions:194 reviews, 229 commits, 251 PRs in 3 years 9 months
Contributions summary:Pirmin's primary focus was on modifying and enhancing the `ibex` RISC-V CPU core. Their work involved replacing hard-coded parameters and signal widths with enumerated types, improving code readability and maintainability. The user also made significant contributions to the bit manipulation instructions within the core, specifically focusing on code comments and the generation and alignment of different data types for the memory interface. Furthermore, they addressed issues in the performance counter CSRs.
risc-vcpuzeroibex32-bit
vogelpi/opentitan
Nov 2019 - Mar 2025
OpenTitan: Open source silicon root of trust
Contributions:109 reviews, 36 PRs, 2393 pushes in 5 years 5 months
root-of-trustrootsilicontrust
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.