Po-yao Chang
Senior Digital ASIC SoC Design Engineer at MediaTek
Taipei, Taiwan
Summary
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Rockstar🎓
Top SchoolPo-yao Chang is a Senior Digital ASIC/SoC Design Engineer with eight years at MediaTek, specializing in high-speed Ethernet and SerDes systems including 56G/112G LR/XSR designs and IEEE 802.3/OIF compliance. He blends digital front-end expertise in low-power design and timing closure with hands-on Rx architecture, link-training and analog calibration algorithm development, and has led cross-team efforts to deliver a 112G XSR SerDes. His background includes large-scale switch fabric work for a 960G data-center switch, giving him systems-level insight into traffic management, buffering and partition integration. Educated in Taiwan and at K.U. Leuven, he brings an international perspective and a track record of collaborating with Tier-1 networking partners to resolve complex analog/digital/FW co-simulation challenges.
8 years of coding experience
4 years of employment as a software developer
Bachelor's degree, Electroinics Engineering, Bachelor's degree, Electroinics Engineering at 國立交通大學Master of Engineering (M.Eng.), Electrical and Electronics Engineering, Master of Engineering (M.Eng.), Electrical and Electronics Engineering at 比利時荷語天主教魯汶大學
Github Skills (48)
reflection10
assembly10
modular10
python10
llvm10
toolchain10
compiler10
swift10
cpp10
rust10
haskell10
clang10
rust-lang9
ruby9
abstraction9
Programming languages (7)
Github contributions (5)
poyaoc97/poyaoc97.github.io
Mar 2020 - Dec 2024
Contributions:118 pushes, 3 branches in 4 years 9 months
poyaoc97/llvm-project-fork
Jun 2023 - Aug 2024
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
Contributions:60 pushes, 13 branches in 1 year 2 months
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