Pouya Fotouhi is a Senior Architect based in San Jose with nine years of experience designing high-performance computing architectures and memory systems, currently tackling AI acceleration at NVIDIA. He holds a Ph.D. in Computer Engineering from UC Davis and has a strong academic-to-industry trajectory that includes research roles at UC Davis and the University of Delaware and an internship at AMD. Pouya is an active contributor to gem5, the widely used computer-system simulator, where he implemented memory-system fixes, new x86 instructions, and PCI device handling for large BARs—work that bridges simulator fidelity and real-world hardware behavior. His expertise spans low-level ISA semantics, cache and memory topology, and practical systems engineering for AI workloads. Colleagues describe him as someone who translates deep research insights into production-facing architecture improvements. He brings a rare combination of rigorous academic training and hands-on systems development that accelerates both simulation fidelity and hardware-aware software.
9 years of coding experience
7 years of employment as a software developer
Doctor of Philosophy - PhD, Computer Engineering, Doctor of Philosophy - PhD, Computer Engineering at University of California, Davis
Master of Science - MS, Computer Engineering, Master of Science - MS, Computer Engineering at University of Delaware
Bachelor of Science - BS, Electrical and Electronics Engineering - Electronics, Bachelor of Science - BS, Electrical and Electronics Engineering - Electronics at University of Isfahan
The official repository for the gem5 computer-system architecture simulator.
Role in this project:
Back-end Developer / Systems Architect
Contributions:16 commits in 1 year 7 months
Contributions summary:Pouya primarily contributed to the gem5 architecture simulator by implementing and modifying core system components related to memory and x86 instruction set architecture. Their work included fixing Ruby memory system topology issues, adding a new slicc statement for handling cache line evictions, and implementing new x86 instructions (movntq/movntdq, adding warnings for movnti and SSE movntps/movntpd instructions). Additionally, the user addressed PCI device configuration, specifically focusing on handling large Base Address Registers (BARs).
Contributions:13 pushes, 1 comment in 1 year 7 months
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