Pranamya Jain
Design Verification Engineer
San Jose, California, United States
Summary
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Senior🎓
Top SchoolPranamya Jain is a design verification engineer with eight years of experience in memory and CPU microarchitecture, currently at Qualcomm after roles at Micron and an Intel CPU formal verification internship. She holds a Computer Engineering master's from UIUC and a BE from BITS Pilani, with deep hands-on experience developing testbenches and model TBs for LPDDR5/LPDDR6 and applying formal methods in out-of-order CPU clusters. Her background blends practical DRAM system verification with formal logic design, enabling robust, scalable hardware validation across both memory and processor domains. Based in San Jose, she’s driven by building verifiable, production-ready silicon and brings a pattern of progressing from internship projects to critical verification contributions on cutting-edge memory and CPU teams.
8 years of coding experience
2 years of employment as a software developer
BITS Pilani, Birla Institute of Technology and ScienceMaster's degree, Master's degree at University of Illinois Urbana-ChampaignGithub contributions (4)
jainpranamya/sap
May 2018 - Jun 2018
Contributions:2 pushes, 1 branch in 3 days
jainpranamya/Pacman-Chase
Aug 2018 - Aug 2018
Contributions:2 pushes, 1 branch in 1 day
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