Pranith K

Mountain View, California, United States

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Summary

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Rockstar

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Top School

Pranith K is a veteran CPU performance architect with 26 years of experience designing and modeling processor microarchitecture and memory subsystems, currently based in Mountain View and holding roles at Arm and NVIDIA. He combines deep academic rigor—a Ph.D. in Computer Architecture from Georgia Tech—with hands-on systems programming in C/C++ and Rust, favoring work "close to the metal." His career spans industry leaders (Google, Qualcomm, Marvell) where he built and validated MMU, L2/LLC, and prefetch/memory models and correlated performance across complex SoC designs. An active open-source contributor, he improved gem5’s caching infrastructure—introducing a generic cache library that enabled novel structures like VFT and DCPT and an associative BTB—highlighting a knack for refactoring large simulators to enable research and product features. Notably, he blends low-level implementation skills with modeling and simulation expertise, making him effective at both prototype research and production-oriented CPU performance engineering.

26 years of coding experience

15 years of employment as a software developer

Ph.D., Computer Architecture, Ph.D., Computer Architecture at Georgia Institute of Technology

B-Tech, Computer Science, B-Tech, Computer Science at Indian Institute of Technology, Kharagpur

English, Hindi, Telugu

Github Skills (11)

simulations10

simulation10

memory-management10

caching10

c-language10

cprogramming-language10

architectures10

architecture10

branch-prediction9

arm8

risc-v8

Programming languages (10)

ShellC++CRustScalaMakefileTeXJupyter Notebook

Github contributions (5)

gem5/gem5

Jun 2020 - Jan 2025

The official repository for the gem5 computer-system architecture simulator.

Role in this project:

Back-end Developer

Contributions:106 reviews, 16 PRs, 159 comments in 4 years 7 months

Contributions summary:Pranith primarily focused on refactoring and improving the gem5 architecture simulator's internal caching mechanisms. They replaced the `AssociativeSet` with a generic cache library, facilitating the implementation of various caching structures like the Value Frequency Table (VFT) and Delta Correlating Prediction Tables (DCPT). These changes involved modifying and introducing new components within the simulator's memory and prefetch modules. Additionally, the user has implemented an associative branch prediction buffer (BTB) using the new cache library.

storedsimulationupstreamsimulatorgem5-simulator

pranith/qemu

Feb 2015 - Aug 2019

Contributions:709 commits, 14 PRs, 550 pushes in 4 years 6 months

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