Prashant Gaikwad
Senior System Software Manager at NVIDIA
San Francisco Bay Area United States
Summary
👤
Senior🎓
Top SchoolPrashant Gaikwad is a Senior System Software Manager with 15 years of experience driving system and embedded software for NVIDIA, currently leading work on Inference Microservices, VLMs, multimodal LLMs and GraphRAG to enable generative AI across video analytics, healthcare and robotics. He combines deep hardware-software expertise from maintaining the open-source NVDLA software stack—where he implemented GEM/DMA support and core HW scheduling—with hands-on chip bring-up on QT, FPGA and simulator platforms. His background in ARM/ARM64 architecture and Linux kernel development includes contributions to the Common Clock Framework upstream, reflecting strong low-level systems credibility. Prashant’s career blends product-focused AI systems leadership with pragmatic embedded engineering rooted in automotive and real-time domains. Colleagues rely on him to translate complex silicon constraints into scalable inference services that move research into production.
15 years of coding experience
15 years of employment as a software developer
Bachelor of Engineering, Information Technology, Bachelor of Engineering, Information Technology at SSJCOESelf-driving Car engineer Nanodegree, Self-driving Car, Self-driving Car engineer Nanodegree, Self-driving Car at Udacity
Github Skills (12)
c1710
firmware10
kernel10
directmemory10
embedded10
abstraction10
device-driver10
c1110
abstraction-layer10
linux-kernel10
sys10
dma10
Programming languages (6)
Github contributions (5)
nvdla/sw
Oct 2017 - Sep 2019
NVDLA SW
Role in this project:
Back-end Developer / System Architect
Back-end Developer / System ArchitectContributions:2 releases, 42 commits, 1 PR in 1 year 11 months
Contributions summary:Prashant focused on implementing and integrating GEM (Graphics Engine Memory) support within the NVDLA (NVIDIA Deep Learning Accelerator) driver, specifically for DMA buffer allocation, mapping, and DMA address retrieval. They implemented core NVDLA HW programming including the engine scheduler for scheduling HW layers on sub-engines. Further contributions involved updating register specifications and adding new features. The user was responsible for registering NVDLA memory for DMA, ensuring memory access by NVDLA, and addressing synchronization issues by modifying the LUT programming strategy.
nvdla
prasshantg/personal
Nov 2013 - Oct 2019
Contributions:60 commits, 59 pushes in 5 years 11 months
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