Pratik Ashar
Principal Engineer, Compilers at Intel Corporation
Mumbai, Maharashtra, India
Summary
👤
Senior🎓
Top SchoolPratik Ashar is a Principal Engineer specializing in compiler design with over 8 years of hands-on experience building and optimizing code generation for Intel’s Gen graphics platform. He has driven key compiler features including spill code cleanup, rematerialization, local value numbering, register allocators and DWARF debug emission, and has practical expertise with the LLVM toolchain. Pratik has repeatedly collaborated with hardware architects to guide path-finding and IP creation, blending low-level implementation with system-level tradeoffs. His background includes designing O2 code generators, LIR frameworks and JIT-friendly register allocation strategies across x86 and GPU targets. Based in Mumbai, he pairs deep compiler internals knowledge with a track record of shipping production-grade compiler passes at Intel. Outside work he pursues endurance challenges—an IRONMAN 70.3 finisher—reflecting the persistence he brings to complex engineering problems.
8 years of coding experience
15 years of employment as a software developer
Master of Science (MS) Electrical and Computer Engineering, Master of Science (MS) Electrical and Computer Engineering at Georgia Institute of TechnologyBachelor of Engineering (BE) Electronics Engineering, Bachelor of Engineering (BE) Electronics Engineering at Veermata Jijabai Technological Institute (VJTI)Diploma Electronics and Video Engineering, Diploma Electronics and Video Engineering at VESP
English
Github Skills (11)
staging10
sycl10
oneapi10
intel10
llvm10
monorepo1
git-mirror1
libgit21
llvm-ir1
subversion1
clang1
Programming languages (2)
Github contributions (4)
intel/intel-graphics-compiler
Mar 2018 - Jan 2023
Contributions:3 reviews, 716 commits, 5 comments in 4 years 10 months
pratikashar/llvm
Feb 2021 - Feb 2021
Intel staging area for llvm.org contribution. Home for Intel LLVM-based projects.
Contributions:5 pushes in 4 days
stagingintelllvm
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