Puneet Goel
Co-Founder And Principal Consultant at Coverify Systems Technology
Gurugram, Haryana, India
Summary
👤
Senior🎓
Top SchoolPuneet Goel is a VLSI and ESL specialist with two decades of industry experience, currently co-founder and principal consultant at Coverify Systems Technology in Gurugram. He has driven spec-to-silicon delivery across seven chip tapeouts in roles spanning design, project leadership, and verification, and he served on the technical review committee for the SystemC P1666-2011 standard. Puneet combines hands‑on expertise in virtual platforms and transaction-level modeling with practical system architecture skills—demonstrated by his contributions to the well-known riscv-dv project where he implemented core modules for randomized instruction generation and signature handling. Comfortable bridging research-grade modeling and production silicon constraints, he has repeatedly translated complex verification requirements into maintainable testbench infrastructure. His background across major semiconductor firms and startups gives him a rare mix of startup agility and large‑product rigor.
14 years of coding experience
5 years of employment as a software developer
Bachelor of Engineering (B.E.), Bachelor of Engineering (B.E.) at Punjab Engineering College
Stackoverflow
878reputation
71kreached
17answers
0questions
Github Skills (19)
systemverilog10
computer-architecture10
architecture10
risc-v10
verification10
instruction-set10
architectures10
configuration-file9
configurations9
testbed9
testbench9
hdl8
asic6
struct6
systemc6
Programming languages (7)
Github contributions (5)
chipsalliance/riscv-dv
Jun 2021 - Apr 2022
Random instruction generator for RISC-V processor verification
Role in this project:
Back-end Developer & System Architect
Back-end Developer & System ArchitectContributions:1 review, 90 commits, 3 PRs in 10 months
Contributions summary:Puneet contributed significantly by adding core modules and configuration files for the RISC-V processor verification project. The primary focus of the commits was on creating the `riscv_signature_pkg` which likely handles testbench communication and result validation, and `riscv_instr_gen_config`, which configures the random instruction generator. The user's work suggests a focus on setting up the program structure and foundational components for random instruction generation and verification of a RISC-V processor.
risc-vriscinstructionverification
puneet/esdl
Apr 2015 - Jul 2015
Verification Language Vlang
Contributions:2 commits, 92 pushes, 4 branches in 2 months
vlangverification
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