Qianfeng Shen
Senior Staff SoC Engineer at Tenstorrent
Old Toronto, Ontario, Canada
Summary
👤
Senior🎓
Top SchoolQianfeng Shen is a Senior Staff SoC Engineer with eight years of experience designing high-performance silicon and FPGA systems, currently driving SoC work at Tenstorrent after architecting low-latency, high-bandwidth interconnects for financial trading at ArchES. He brings full‑stack networking hardware expertise—from transceiver-level design through Ethernet, UDP/IP and TCP/IP stacks to PCIe logic—paired with a PhD-level grounding in computer engineering from the University of Toronto. Known for turning complex requirements into shipping silicon, he combines IC and FPGA design fluency with systems-level architecture and a knack for optimizing for latency and reliability. Based in Toronto, he has a track record of impactful industry work and early recognition during his Cadence internship for innovation. Colleagues can expect a pragmatic engineer who bridges research rigor with production delivery and is open to new opportunities.
8 years of coding experience
4 years of employment as a software developer
Doctor of Philosophy - PhD, Computer Engineering, Doctor of Philosophy - PhD, Computer Engineering at University of Toronto
Github Skills (39)
axi-stream9
stream9
redundancy8
cyclic8
iverilog7
udp7
xilinx7
fpga6
fifo6
driver6
music6
serve6
fabric6
vivado6
cycle6
Programming languages (7)
Github contributions (5)
QianfengClarkShen/easy_fifo
Mar 2020 - Jan 2021
a zero latency axi4-stream fifo
Contributions:40 commits, 2 PRs, 32 pushes in 9 months
zeroaxi4latencyfifonodejs
QianfengClarkShen/GULF-Stream
Mar 2019 - Jan 2020
100G Udp Link For axi Stream
Contributions:59 commits, 7 PRs, 38 pushes in 9 months
axiaxi-streamstreamlinkudp
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