Summary
Qiao Bin is a senior logic design engineer based in Hangzhou with nine years of professional experience and a master's in Circuits and Systems. He has led RTL design and verification of high-performance crypto engines (AES, 3DES, ZUC, Snow3G), compression/decompression IPs and various interface modules, delivering multi-hundred‑k‑gate cores and FPGA prototypes. At Exar Corporation he architected and debugged complex enc/dec, compression and peripheral blocks, blending hands‑on RTL implementation with system-level verification. A strong mathematical background (national 1st-class Math Olympiad prize) informs his methodical approach to algorithmic hardware design and optimization.
9 years of coding experience
Master's degree, Circuit and System, Master's degree, Circuit and System at Hangzhou Dianzi University
Bachelor's degree, Electrical and Electronics Engineering, Bachelor's degree, Electrical and Electronics Engineering at Zhejiang University