Summary
Qiaoyi Liu is a compiler engineer and PhD-trained researcher with six years of experience at the intersection of compilers and domain-specific accelerator architecture, currently contributing to AWS Neuron at Annapurna Labs. Her Stanford research under Prof. Mark Horowitz focused on polyhedral compilation, schedule and memory-mapping optimizations for tensor accelerators and on-chip memory microarchitecture for reconfigurable hardware. She has industrial research experience at NVIDIA, Meta, Samsung, and DeePhi, applying dataflow and hardware implementation techniques to sparse DNNs, 3D reconstruction, and near-storage computing for video analytics. Known for bridging high-level synthesis and hardware-aware compiler design, she brings a practical track record of moving academic innovations toward production-grade accelerator toolchains.
6 years of coding experience
6 years of employment as a software developer
Exchange Student, Electrical and Electronics Engineering, Exchange Student, Electrical and Electronics Engineering at North Carolina State University
Electrical and Electronics Engineering, Electrical and Electronics Engineering at Tsinghua University
Doctor of Philosophy - PhD, Electrical and Electronics Engineering, Doctor of Philosophy - PhD, Electrical and Electronics Engineering at Stanford University
English, Chinese