Quan Nguyen
Engineer at zeroRISC
Cambridge, Massachusetts, United States
Summary
🤩
Rockstar🎓
Top SchoolQuan Nguyen is an engineer who bridges hardware and software with 14 years of experience designing everything from polygon-level circuits to Linux kernel patches and cloud deployments. He earned a Ph.D. from MIT for novel pipeline-parallel techniques that sped sparse graph, linear algebra, and database workloads—work that produced tools like Pipette, Fifer, and the Phloem compiler and yielded up to 40× gains on reconfigurable architectures. His industry roles span postdoc work porting Verilator for specialized hardware to senior architecting of AI/HPC systems at Samsung and current engineering at zeroRISC, and he has contributed to the widely used Spike RISC-V ISA simulator by adding half-precision FP support and correcting control-flow semantics. Pragmatic and collaborative, Quan invests in enabling colleagues through teaching, tooling, and mentorship, and he uniquely combines deep RTL prototyping experience with production-facing OS and cloud skills.
13 years of coding experience
11 years of employment as a software developer
B.S. Electrical Engineering and Computer Sciences, B.S. Electrical Engineering and Computer Sciences at University of California, BerkeleyPh.D. Electrical Engineering and Computer Science, Ph.D. Electrical Engineering and Computer Science at Massachusetts Institute of Technology
Github Skills (9)
risc-v10
c-language10
cprogramming-language10
float329
sys9
floating-point9
embedded9
assembly8
assembler8
Programming languages (5)
Github contributions (5)
riscv-software-src/riscv-isa-sim
Jul 2013 - Apr 2014
Spike, a RISC-V ISA Simulator
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:9 commits in 9 months
Contributions summary:Quan primarily contributed to the RISC-V ISA simulator by addressing issues related to the `eret` instruction and adding support for half-precision floating-point instructions. These contributions involved modifying the instruction set architecture simulation to improve accuracy and functionality. The user also incorporated updates from external repositories for opcode definitions and implemented specific half-precision related opcodes within the simulator.
risc-visariscvriscv32simulator
qmn/dewey
Apr 2016 - Apr 2018
Contributions:105 commits, 1 branch in 1 year 11 months
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