Quentin Ducasse is a postdoctoral researcher and PhD graduate in Computer Science with eight years of experience at the intersection of VM security and hardware-enforced protections. He specializes in co-designing lightweight RISC-V security extensions for JIT-compiled high-level language VMs and is currently designing a dynamic information flow tracking co-processor at CentraleSupélec. During his PhD he ported the Pharo VM JIT to RISC-V and prototyped a hardware security mechanism in the CVA6 core, producing peer-reviewed publications. He also brings practical QA and test automation experience from contributing RISC-V and ARM64 tests to the widely used Unicorn CPU emulator, underscoring his cross-layer expertise from emulation to silicon. Based in Rennes, France, Quentin blends hands-on prototyping with rigorous research to advance pragmatic, hardware-assisted software security.
Contributions:1 review, 8 commits, 2 PRs in 6 months
Contributions summary:Quentin focused on adding and enhancing unit tests within the Unicorn CPU emulator framework. Their contributions include writing new test cases for RISC-V and ARM64 architectures, covering functionality like basic operations, register manipulation, and code patching. They also implemented tests for jump hook addresses and ensured the correct behavior of code patching mechanisms with cache flushing. The user demonstrated expertise in testing different CPU architectures supported by Unicorn.
:crossed_swords: Simplified Schotten Totten cardgame with GUI and IAs for python.
Contributions:16 PRs, 62 pushes, 1 branch in 1 year
pythoniascardgamesimplifiedgui
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Quentin Ducasse - Postdoctoral Researcher at CentraleSupélec