Rafael Possignolo
Senior CPU Architect at AheadComputing
Hillsboro, Oregon, United States
Summary
👤
Senior🎓
Top SchoolRafael Possignolo is a Senior CPU Architect with 11 years of experience blending academic rigor and industry research to build high-performance accelerators and digital-design productivity tools. Currently at AheadComputing after five years as a Research Scientist at Intel, he specializes in automated pipeline optimizations, interactive synthesis flows, and EDA techniques that speed RTL-to-hardware iteration. His PhD work and internships at Xilinx produced practical pipeline-analysis and interconnect automation tools, reflecting a consistent focus on making complex hardware design flows more productive. An active contributor to the Yosys open synthesis suite, he has improved Verilog backend handling and equivalence checking to better manage memory offsets and signal mapping—demonstrating both low-level rigor and open-source craftsmanship. Based in Hillsboro, Oregon, he combines deep circuit-level insight (including voltage stacking research) with hands-on engineering to bridge research prototypes and production accelerators. Notably, his background spans quantum co-processor design to many-core NoC emulation, revealing a long-standing appetite for ambitious, system-level hardware challenges.
11 years of coding experience
6 years of employment as a software developer
Engineer, Computer Engineering, Engineer, Computer Engineering at USP - Universidade de São PauloMSc., Embedded Systems, MSc., Embedded Systems at Paris-Sud University (Paris XI)University of California Santa CruzMaster of Science (MSc), Electrical Engineering, Master of Science (MSc), Electrical Engineering at Universidade de São Paulo / USPEngineer, Embedded Systems, Engineer, Embedded Systems at Ecole Nationale Supérieure de Tecniques Avancées
Portuguese, English, French, Spanish, German
Github Skills (8)
rt10
yosys10
verilog10
backend10
back-end-development10
cprogramming-language9
c-language9
computer-engineering8
Programming languages (6)
Github contributions (5)
YosysHQ/yosys
Oct 2018 - Oct 2018
Yosys Open SYnthesis Suite
Role in this project:
Backend Developer
Backend DeveloperContributions:7 commits, 1 PR, 5 comments in 3 days
Contributions summary:Rafael contributed to the Yosys Open SYnthesis Suite by modifying the Verilog backend and the equivalence checking passes. Their work includes adding offset information to memory declarations and modifying the equivalence checking process to handle signal mapping more effectively. The commits also address code style issues and refactor the handling of signal bits within the equivalence checking process.
yosys
masc-ucsc/anubis
Jun 2017 - Nov 2018
The ANUBIS benchmark suite for Incremental Synthesis
Contributions:22 commits, 21 pushes, 1 branch in 1 year 5 months
incrementalbenchmark-suiteanubissynthesizersynthesis
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