Rafal Baranowski
Senior Expert ASIC Design Verification
Pfullingen, Baden-Württemberg, Germany
Summary
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Senior🎓
Top SchoolRafal Baranowski is a Senior Expert in ASIC Design Verification with 12+ years of experience delivering safety-critical mixed-signal and digital SoCs, currently leading verification for automotive ASICs at Bosch. He combines deep practical expertise in SystemVerilog UVM, formal methods, AMS verification and modelling with hands-on skills in SystemC, VHDL and verification languages (SVA/PSL), and brings solid software tooling experience in Python, C/C++ and scripting. His background spans academic research—earning a summa cum laude doctorate—and industry roles where he developed IJTAG-related test and protection algorithms, ATPG and fault-simulation techniques. Skilled in competence management and coordinating external providers, he also recruits and mentors verification talent while steering verification strategy for safety metrics and fault simulation. An enthusiast of hardware security and machine learning, Rafal bridges rigorous formal methods with practical chip-level verification to improve reliability and testability in safety-critical systems.
12 years of coding experience
11 years of employment as a software developer
M.Sc., Electronics and Telecommunications, with honors, M.Sc., Electronics and Telecommunications, with honors at Silesian University of Technology (Gliwice, Poland)Dr. rer. nat., Informatik, summa cum laude, Dr. rer. nat., Informatik, summa cum laude at University of Stuttgart
English, German, Polish
Github Skills (1)
threshold6
Programming languages (1)
Github contributions (5)
rbaranowski/not-num-ex
Jul 2016 - Sep 2016
Contributions:10 commits, 6 pushes, 1 branch in 1 month
rbaranowski/not
Dec 2016 - Feb 2022
Norrowest-Over-Threshold Change-Point Detection
Contributions:2 pushes, 1 branch in 5 years 3 months
change-pointthresholdpointchange-point-detectionpoint-detection
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