Rafał Kapuścik
Senior Software Engineer at Antmicro
Wroclaw Metropolitan Area Poland
Summary
🤩
Rockstar🎓
Top SchoolRafał Kapuścik is a Senior Software Engineer based in the Wroclaw area with six years of professional experience spanning embedded systems, Linux kernel work, and tooling for hardware-adjacent software. At Antmicro he progressed from software engineer to senior roles, applying deep C/C++ and embedded Linux expertise to complex hardware bring-up and driver maintenance. He has a strong hardware background from medical and DSP projects and early PCB work, giving him a practical systems perspective that informs his software choices. An active contributor to the Verible SystemVerilog tooling project, Rafał focuses on code quality and formatting improvements—work that improves readability and consistency for hardware description languages. He combines academic training in electronics from Politechnika Wrocławska with hands-on experience in Yocto, ARM, and test automation to deliver reliable, maintainable firmware and developer tooling.
6 years of coding experience
4 years of employment as a software developer
Magister inżynier (Mgr inż.) Elektronika, Magister inżynier (Mgr inż.) Elektronika at Politechnnika WrocławskaInżynier (Inż.) Elektronika i telekomunikacja, Inżynier (Inż.) Elektronika i telekomunikacja at Politechnika Wrocławska
Github Skills (9)
linter10
parserator10
formatter10
parser10
lint10
systemverilog10
formatters10
stylelint10
code-formatting10
Programming languages (7)
Github contributions (5)
chipsalliance/verible
Feb 2020 - Jun 2021
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Role in this project:
Software Engineer (Focus on Code Quality and Formatting)
Software Engineer (Focus on Code Quality and Formatting)Contributions:3 reviews, 19 commits, 30 PRs in 1 year 4 months
Contributions summary:Rafał made several contributions focused on improving code quality and formatting within the Verible project. Their work included implementing a style rule for interface naming conventions, enhancing the formatter for bind directives and ternary expressions, handling cycle/delay ranges in formatting, and improving concatenation expressions' partitioning. They also addressed formatting issues with initializer lists and coverpoints, demonstrating a focus on consistent code style and readability.
lintersystemverilogdeveloper-toolsparserformatter
antmicro/verilator
Feb 2020 - Feb 2022
Contributions:200 reviews, 2753 commits, 130 PRs in 2 years
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