Rafał Kołucki
Firmware Engineer In Security And Transport at Solidigm
Gdańsk, Pomeranian Voivodeship, Poland
Summary
👤
Senior🎓
Top SchoolRafał Kołucki is a firmware engineer specializing in security and transport with 11 years of professional experience and a five-year focus on low-level software and embedded systems. Based in Gdańsk, he blends hands-on RTL and FPGA work (Verilog, Migen/Python) with C programming for RISC-V and POSIX environments, plus CI/unit test and occasional C# development. His open-source contributions to the popular LiteX ecosystem—adding Wishbone SRAM burst support and tests—demonstrate deep hardware-software integration skills and an ability to improve SoC interconnect semantics. At Antmicro he moved fluidly across full-stack embedded responsibilities from FPGA design to firmware, and now applies that breadth to security and transport firmware at Solidigm. Colleagues would describe him succinctly as a "computer systems plumber": pragmatic, detail-oriented, and effective at making complex low-level systems work reliably together.
11 years of coding experience
4 years of employment as a software developer
Inżynier (Inż.), Elektronika i telekomunikacja, Inżynier (Inż.), Elektronika i telekomunikacja at Politechnika Łódzka
Polish, English
Github Skills (10)
fpga10
ram10
system-on-chip10
hardware10
vhdl9
system-design9
vhd9
hdl9
verilog9
testing8
Programming languages (16)
Github contributions (5)
enjoy-digital/litex
Feb 2022 - Jul 2022
Build your hardware, easily!
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:9 reviews, 9 commits, 11 comments in 5 months
Contributions summary:Rafał primarily contributed to the Litex repository, focusing on hardware design and integration, specifically for FPGA-based systems. Their commits centered on the Wishbone interconnect, adding burst cycle support to SRAM and moving related options to the SoC bus handler classes. They also introduced tests for Wishbone SRAM burst cycles. These changes demonstrate a deep understanding of hardware architecture and low-level system design.
hardwarefpgasystem-on-chip
antmicro/wishbone-interconnect-burst-mode-benchmark
Dec 2021 - Sep 2022
Contributions:65 commits, 18 pushes, 2 branches in 9 months
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