Rafmag Cabrera

R&D Electronics Engineer at Sandia National Laboratories

Albuquerque-Santa Fe Metropolitan Area United States
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Summary

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Senior
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Top School
Rafmag Cabrera is an R&D electronics engineer with nine years of experience specializing in compound semiconductor microelectronics, MEMS, and flexible bio-integrated devices. He leads HBT design work at Sandia National Laboratories and brings deep hands-on expertise across mask design, cleanroom fabrication, and electrical characterization from prior roles at MIT Lincoln Laboratory and Michigan State. His PhD-trained background blends materials science, smart-material actuators, and microfabrication with practical system-level instrumentation including automated microfluidics and fuel-cell testbeds. Notably, he has developed integrated processes for CNT and Nafion patterning on flexible substrates and built custom measurement systems that couple mechanical, acoustic, and electrical models to real prototypes. Based in the Albuquerque–Santa Fe area, he combines research rigor with production-oriented process development and a track record of moving devices from concept to tested hardware. He is comfortable spanning design, fabrication, and test—often optimizing fabrication flows that become standardized in the lab.
code9 years of coding experience
job5 years of employment as a software developer
bookBachelor of Science (BS), Electrical Engineering, Bachelor of Science (BS), Electrical Engineering at Universidad de Puerto Rico
bookDoctor of Philosophy (Ph.D.), Electrical Engineering, Doctor of Philosophy (Ph.D.), Electrical Engineering at Michigan State University
languagesEnglish, Spanish
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Github Skills (17)

netlist9
vlsi9
clipping9
verilog9
pascal9
delphi9
polygon9
cpp8
inflate8
asic8
boolean-operations8
vhdl8
algorithm8
csharp8
geometry8

Programming languages (3)

C++CRust

Github contributions (5)

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rafmag/xschem

Aug 2022 - Feb 2026

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Contributions:94 pushes in 3 years 7 months
vhdlcircuitsreusevlsianalog
rafmag/Clipper2

Apr 2022 - Dec 2022

Polygon Clipping and Offsetting library
Contributions:4 pushes, 1 branch in 8 months
polygon-clippingclippingpolygon
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