Raghav Medicherla is an ASIC engineer and NC State Computer Engineering master's candidate with four years of experience building and verifying processor-related systems. He interned on AMD’s ROCm compiler team, contributing LLVM VFS write support and adapting offload bundling for on-disk output backends to improve clang driver performance and runtime symbol resolution. Now at Cisco, he applies compiler-aware hardware design and verification skills to ASIC projects, blending low-level toolchain insight with silicon-focused engineering. His background includes hands-on research experience at DRDO and a BTech in ECE, reflecting a strong mix of embedded systems, compilers, and architecture expertise that often reveals toolchain-level optimizations beyond typical RTL work.
3 years of coding experience
Bachelor of Technology - BTech, Electronics and Communication Engineering, 8.12, Bachelor of Technology - BTech, Electronics and Communication Engineering, 8.12 at Gitam University, Hyderabad
Master's degree, Computer Engineering, 3.74, Master's degree, Computer Engineering, 3.74 at North Carolina State University
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.
Contributions:3 reviews, 1 PR, 7 pushes in 2 months
Contributions:4 PRs, 23 pushes, 4 branches in 1 day
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