Rahul Bramandlapalli
Senior Software Development Engineer at AMD
Telangana, India
Summary
👤
Senior🎓
Top SchoolRahul Bramandlapalli is a Senior Software Development Engineer with about six years of hands-on experience building runtime environments, device drivers, and tooling for card-based FPGA/AIE platforms. He specializes in low-level C/C++ development, kernel device drivers, Linux OS support, and automation using Python and shell tooling, with practical expertise in build systems like Makefiles and CMake. At Xilinx and now AMD, he has contributed to the widely used XRT runtime—improving mmap handling, xclbin loading, and cross-platform support including RHEL variants and Windows gtest integration. He combines backend and DevOps sensibilities to keep binaries and libraries portable across Linux flavors and edge platforms. Based in Telangana, India, he pairs an ECE background from NIT Warangal with a pragmatic focus on reliability and cross-OS compatibility that often shows up as behind-the-scenes infrastructure fixes rather than flashy features.
6 years of coding experience
4 years of employment as a software developer
Bachelor's degree, Electrical, Electronics and Communications Engineering, Bachelor's degree, Electrical, Electronics and Communications Engineering at National Institute of Technology Warangal
Github Skills (11)
c-language10
cmake10
cprogramming-language10
linux-kernel10
devops9
fpga9
rhel9
gt8
yocto8
mstest8
python7
Programming languages (3)
Github contributions (5)
Xilinx/XRT
Jan 2020 - Jan 2023
Run Time for AIE and FPGA based platforms
Role in this project:
Back-end Developer & DevOps Engineer
Back-end Developer & DevOps EngineerContributions:144 reviews, 133 commits, 222 PRs in 3 years
Contributions summary:Rahul's commits primarily focus on enhancing the Xilinx Run Time (XRT) for AIE and FPGA platforms. The contributions include adding support for Google Test (gtest) for Windows, fixing documentation related to the yocto build process, and addressing issues related to mmap functionality. They also implemented infrastructure improvements, such as adding support for xbutil2 on edge platforms and resolving xclbin loading failures, and support of RHEL 8.1, 8.2, 8.5, 8.6 OS versions.
vitisxilinxlinux-kernelxrtfpga
rbramand-xilinx/XRT
Oct 2019 - Apr 2025
Xilinx Run Time for FPGA
Contributions:11 PRs, 596 pushes, 115 branches in 5 years 6 months
xilinxvivadofpga
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