Rahul Patil
Digital Design Engineer at Intel Corporation
Bengaluru, Karnataka, India
Summary
👤
Senior🎓
Top SchoolRahul Patil is a Digital Design Engineer with nine years of hands-on RTL design, verification, and FPGA validation experience, currently contributing at Intel after roles at Chelsio, Eximius, and Mobiveil. He specializes in high-speed interfaces and protocols—notably PCIe transaction and data link layers—and has implemented and validated designs on Zynq Ultrascale+ platforms. Rahul has a strong verification background using RAL models and Cadence NC-Sim, and practical synthesis experience with Design Compiler and Vivado. His M.Tech in VLSI Design underpins work on AMBA-AHB and MIPI-DSI modules early in his career, reflecting a blend of academic depth and applied engineering. Colleagues describe him as a pragmatic problem-solver who pairs protocol-level understanding with FPGA bring-up skills, often surfacing subtle timing and link-level issues before silicon. He is also a CS grad affiliate with UCSD on GitHub, signaling ongoing engagement with broader software and systems topics beyond pure RTL.
9 years of coding experience
5 years of employment as a software developer
Master of Technology - MTech, VLSI Design, Master of Technology - MTech, VLSI Design at SRM University
Github Skills (28)
top2vec8
sentence-transformers7
text-search7
topic-modeling6
word-embeddings6
nlp5
bert5
gensim5
machine-learning4
natural-language-processing4
embedded4
sentence-similarity4
sentence-embeddings3
issue-tracking3
semantic-search2
Programming languages (4)
Github contributions (5)
rahup97/theta-maze
May 2017 - Jan 2019
Contributions:3 commits, 2 pushes, 1 branch in 1 year 8 months
rahup97/smart-parking
May 2017 - Jun 2019
Contributions:19 commits, 14 pushes, 3 branches in 2 years 1 month
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