Raiyyan Masumdar
Senior SoC Verification Engineer
Austin, Texas, United States
Summary
👤
Senior🎓
Top SchoolRaiyyan Masumdar is a Senior SoC Verification Engineer with eight years of experience validating processor cores, high-speed interfaces, and complex on-chip fabrics across companies like Arm, Analog Devices, and Intel. He combines deep SystemVerilog/UVM testbench expertise with system-level modeling in SystemC/TLM to enable early software bring-up and performance-driven topology tweaks (notably optimizing a third-party NoC for 5G transceiver targets). Raiyyan has driven verification strategy end-to-end—from verification plans and reference models to constrained-random stimulus and coverage-driven scoreboards—and has integrated vendor VIPs and UPF-aware checks into production flows. A California State University MS grad based in Austin, he also brings research experience in image-processing algorithms and a track record of building reusable verification infrastructure that teams across organizations rely on.
8 years of coding experience
6 years of employment as a software developer
Higher Secondary Education, Higher Secondary Education at Rajarshi Shahu Mahavidyalaya (Autonomous), LaturSenior Secondary Class, Senior Secondary Class at Shri Bankatlal Lahoti English School, LaturBachelor of Engineering (BE) Electrical Electronics and Communications Engineering, Bachelor of Engineering (BE) Electrical Electronics and Communications Engineering at KJ Somaiya College of EngineeringMaster of Science - MS Electrical Engineering Digital Hardware Design, Master of Science - MS Electrical Engineering Digital Hardware Design at California State University, NorthridgePG Diploma in Advanced VLSI Design and Verification VLSI Designing, PG Diploma in Advanced VLSI Design and Verification VLSI Designing at Maven SiliconElectrical Engineering and Computer Science, Electrical Engineering and Computer Science at MIT Open Course WareA Short Term Diploma Course on VLSI Designing Front End VLSI Designing, A Short Term Diploma Course on VLSI Designing Front End VLSI Designing at Front End VLSI Designing
English, Urdu, Marathi, Hindi
Github Skills (12)
bit8
32-bit8
hardware8
bus7
risc7
openembedded7
risc-v7
cpu6
computer-engineering6
verification4
uvm4
verilog2
Programming languages (1)
Github contributions (5)
raiyyanfaisal09/AXI_Verification
Apr 2018 - Sep 2020
Contributions:1 PR, 35 pushes, 2 branches in 2 years 6 months
axiverilogbussystem-verilogverification
muguang123/AXI_Verification
Apr 2018 - Apr 2018
Verification AXI-4 bus standard using UVM and System Verilog
Contributions:35 commits in 1 day
axiverilogbussystem-verilogpython3
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