Summary
Raj Shah is a Ph.D. Research Scholar with eight years of experience specializing in semiconductor physics, nano-transistor modeling, and ultra-low-power circuit design. Based at SVNIT Surat, he completed a thesis on designing SET and a novel Hybrid SETMOS technique for ultra-low-power VCOs, blending single-electron transistor concepts with CMOS for practical circuit implementations. His background combines rigorous academic research in nanodevices with hands-on VLSI verification training and M.Tech expertise in VLSI design. Actively seeking industry roles in semiconductors, he brings deep device-level insight useful for power-constrained applications like IoT and edge devices. Notably, his work bridges theoretical device modeling and circuit-level simulation, enabling translational solutions from lab concepts to chip-ready architectures.
8 years of coding experience
Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering, 8.09/10, Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering, 8.09/10 at Gujarat Technological University
Trainee for system verilog course, VLSI testing and verification, Trainee for system verilog course, VLSI testing and verification at DKOP Labs Pvt Ltd
Master of Technology (M.Tech.), VLSI, 8.20/10, Master of Technology (M.Tech.), VLSI, 8.20/10 at Thapar Institute of Engineering and Technology
Doctor of Philosophy - PhD, Nanodevices, Single Electron transitors, Hybrid CMOS-SET circuits for low power appliocation, Doctor of Philosophy - PhD, Nanodevices, Single Electron transitors, Hybrid CMOS-SET circuits for low power appliocation at Sardar Vallabhbhai National Institute of Technology, Surat
English, Hindi, Gujarati