Rajat Sarkari
Senior Software Development Engineer at AMD
Noida, Uttar Pradesh, India
Summary
👤
Senior🎓
Top SchoolRajat Sarkari is a Senior Software Development Engineer with nine years of experience building high-performance hardware-adjacent software at AMD and Cadence, blending expertise in HLS, Verilog and machine learning frameworks like TensorFlow and PyTorch. He has progressed through multiple engineering levels at AMD, delivering production-ready solutions that bridge RTL, FPGA acceleration and software stacks. His open-source contributions include backend work on Xilinx Vitis FPGA examples—optimizing memory alignment and kernel interfacing for compute acceleration—which highlights practical skills in C++, OpenCL and data-type tradeoffs. Based in Noida, he combines rapid, accurate delivery with a collaborative mindset and a diploma-to-bachelor’s educational path grounded in digital and electronics engineering.
9 years of coding experience
4 years of employment as a software developer
Bachelor’s Degree, Electrical, Electronics and Communications Engineering, Bachelor’s Degree, Electrical, Electronics and Communications Engineering at Maharaja Agrasen Institute Of TechnologyHigh School, High School at St. Joseph's Inter CollegeDiploma, Digital Electronics, Diploma, Digital Electronics at Ambedkar Institute Of Technology
English, German, Hindi
Github Skills (8)
opencl10
vitis10
c-language10
cprogramming-language10
xilinx10
memory-management9
data-structures8
data-structure8
Programming languages (3)
Github contributions (5)
Xilinx/Vitis_Accel_Examples
Apr 2019 - Feb 2021
Vitis_Accel_Examples
Role in this project:
Back-end Developer
Back-end DeveloperContributions:120 commits, 20 pushes in 1 year 10 months
Contributions summary:Rajat appears to be working on Xilinx FPGA based examples. The commits show modifications to C++ code, specifically within the `fpga_kmeans.cpp` file. The code involves memory allocation, data alignment and interfacing with OpenCL kernels, indicating a focus on accelerating computations on FPGA hardware. The changes also indicate a potential shift between float and integer data types.
vitisxilinxaccelfpga-programmingacap
rajatsarkari/imad-2016-app
Sep 2016 - Nov 2016
Contributions:223 pushes, 2 branches in 2 months
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