Rajdeep Mondal is a seasoned ASIC/Layout Design Engineer with 13 years of experience, currently driving sub-system testbench development for GPU caches at AMD in Canada. He brings deep expertise in UVM-based verification, SystemVerilog, and protocol verification (MIPI CSI-2 over D-PHY, AXI/APB) from senior roles at NVIDIA and AMD, and has led teams building self-checking, coverage-driven environments for compression/decompression and camera subsystems. Rajdeep pairs practical silicon bring-up and FPGA/emulation experience with scripting and automation skills (Perl/Python, Shell), enabling fast debug of high-speed data-transfer issues and pad-model integration. His academic background in reconfigurable computing and publications from IISc hint at a strong research-to-product orientation, and he’s known for improving verification methodology and creating reusable UVM libraries that accelerate multi-block SoC signoff.
13 years of coding experience
12 years of employment as a software developer
ME, Microelectronics, ME, Microelectronics at Indian Institute of Science
HS, Science, Additional: Biology, HS, Science, Additional: Biology at South Point High School
BE, Electronics & Communication Engg., BE, Electronics & Communication Engg. at Jadavpur University
Digital Design2 (computer organization), Digital Design2 (computer organization) at Stanford University
Contributions:5 commits, 16 pushes, 2 comments in 6 years 10 months
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.