Raman Jana
Hardware Engineer - Self Driving & Robotics at Tesla
Austin, Texas, United States
Summary
👤
Senior🎓
Top SchoolRaman Jana is a PMTS and GPU performance engineer with 8+ years focused on co-optimizing hardware-software stacks for machine learning across AMD architectures. He has shipped highly performant GEMM kernels and fused-operation kernels (flash attention, MLP+activation) on AMD MI, working with Triton, HIP, and ML compiler teams to reach assembly-like performance. At AMD he shapes ML architecture and numerical-precision strategies (fp4/fp6/fp8) and builds distributed language-model performance models to inform future hardware design. His open-source contributions to ROCm/Tensile—optimizing assembly codegen, DirectToLDS and DGEMM paths—underscore a deep, practical mastery of GPU memory and compute tradeoffs. Previously he led CPU architecture teams at Intel and briefly worked on robotics/hardware architecture at Tesla, giving him rare breadth across CPU/GPU and system-level design. Based in Austin, he combines low-level kernel craft with architectural vision to accelerate real-world ML workloads.
8 years of coding experience
9 years of employment as a software developer
Government College of Technology, Coimbatore
Github Skills (22)
assembly10
performance-monitor10
performance-analytics10
gpgpu10
amd10
performance-measurement10
hip10
gemfire10
performance-analysis10
gpu10
assemble10
assembler10
accelerated-computing10
performance-tuning10
performance-monitoring10
Programming languages (3)
Github contributions (5)
ROCm/Tensile
Jan 2019 - Aug 2021
Stretching GPU performance for GEMMs and tensor contractions.
Role in this project:
Back-end Developer & Performance Engineer
Back-end Developer & Performance EngineerContributions:17 reviews, 45 commits, 89 PRs in 2 years 7 months
Contributions summary:Raman primarily contributed to the Tensile project by modifying the `KernelWriterAssembly.py` file, indicating a focus on the assembly code generation process. Their work involved implementing and optimizing features related to the TransposeLDS functionality and DirectToLDS, a technique used for GPU memory access. They also made changes related to DGEMM (double-precision GEMM) support, suggesting an emphasis on optimizing performance for matrix operations within the AMD ROCm platform.
amdpythontensorhipauto-tuning
ramjana/composable_kernel
May 2022 - Sep 2024
Composable C++ Template abstractions for implementing Tensor contraction operators (GEMM, iGEMM).
Contributions:2 PRs, 15 pushes, 3 branches in 2 years 3 months
tensor-contractioncpptensorcomposablecontraction
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