Ramdas Mozhikunnath
Principal Engineer at Qualcomm
Bengaluru, Karnataka, India
Summary
👤
Senior🎓
Top SchoolRamdas Mozhikunnath is a Principal Engineer and verification specialist with over 25 years of end-to-end experience crafting verification strategy and execution for microprocessor cores, coherency fabrics, and memory subsystems across RISC-V, ARM and x86 platforms. He has repeatedly built and led high-performing verification teams—driving methodology adoption, testbench architecture, and coverage-driven closure from unit to system level at companies including Intel, AMD, AppliedMicro, Ventana (acquired by Qualcomm) and Qualcomm. A hands-on engineer, he authored training labs and SystemVerilog examples used for teaching and created the VerificationExcellence portal that delivers courses, blogs and practical labs to upskill engineers. He is co-author of a well-regarded industry book on VLSI verification interviews and regularly contributes to academia through workshops and career talks. Known for tackling complex subsystems (caches, coherency, IOMMU, chiplet interfaces) and enabling early SW/HW co-verification, he blends deep technical debugging with team mentorship. Based in Bengaluru, he combines production-proven silicon bring-up experience with a passion for teaching and open-source training material.
11 years of coding experience
14 years of employment as a software developer
Bachelor of Engineering (B.E.) Electrical Electronics and Communications Engineering, Bachelor of Engineering (B.E.) Electrical Electronics and Communications Engineering at National Institute of Technology Calicut
Stackoverflow
86reputation
14kreached
6answers
1question
Github Skills (15)
verification10
formal-verification10
systemverilog10
hardware10
hardwareid10
ethernet9
verilog9
digital-design8
fifo7
memory-management6
caching6
cpu-architecture6
constraint6
cpu-cache6
logic6
Programming languages (2)
Github contributions (5)
VerificationExcellence/SystemVerilogReference
Jun 2014 - Jun 2016
training labs and examples
Role in this project:
Verification Engineer
Verification EngineerContributions:43 commits, 23 pushes, 1 comment in 2 years
Contributions summary:Ramdas primarily focused on creating and modifying SystemVerilog code within the `systemverilogreference` repository, which is described as containing training labs and examples. Contributions included creating new SystemVerilog files for examples, such as an Ethernet switch design, and making modifications to existing code for both data types and basic systemverilog concepts. They also added supporting files like packet, monitor, and checker classes for ethernet examples.
pythondata-sciencetlamachine-learningtraining
VerificationExcellence/UVMReference
Jul 2014 - Jan 2016
Reference examples and short projects using UVM Methodology
Contributions:19 commits, 1 push in 1 year 6 months
tuplemethodologyshortprogram-analysisuvm
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.