Summary
Randy Thomas is an experienced ASIC/SoC physical design engineer and founder with over 25 years in semiconductor design and a proven record of 50+ tape-outs. As owner of Ranomco Holdings he helps companies recover schedule risk and talent gaps by delivering RTL-to-GDSII flows, timing closure, DRC/LVS sign-off, and system integration for complex mixed-signal chips. His background spans leadership and hands-on roles at Renesas, NEC, Lockheed Martin, InnoPhase, and Intel, where he streamlined IP verification flows and cut multi-hour processes down to minutes. He blends deep toolchain expertise (Cadence, Calibre, Pegasus, Jasper, Tempus, Voltus) with automation skills in TCL, Python, Perl, YAML, and Make to accelerate delivery and improve first-pass silicon success. Based in Daphne, Alabama, he pairs technical breadth—from low-power multi-voltage designs with ARM/RISC-V cores to package and ATE considerations—with practical project management across distributed teams. An adaptive problem-solver, he often acts as the bridge between RTL, verification, analog, and EDA vendors to fix show-stopping issues quickly.
10 years of coding experience
26 years of employment as a software developer
BSEE Electrical Engineering, BSEE Electrical Engineering at University of Florida
English, python, perl, tcl, yaml, verilog, vhdl, c, c++, stylus cui, bash, make, systemverilog, uvm, rust