Reed Terdal
Senior Silicon Design Engineer at AMD
Burlington, Massachusetts, United States
Summary
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Senior🎓
Top SchoolReed Terdal is a Senior Silicon Design Engineer with eight years of experience designing high-performance CPU front-end microarchitecture, currently focusing on PPA-driven enhancements at AMD. He has deep RTL expertise in branch prediction and instruction cache development for Zen cores and a strong background in embedded systems, sensor calibration, and RTOS-driven hardware-software integration from RIT and industry co-ops. Reed combines academic teaching experience in C programming with hands-on PCB, driver, and calibration tool development for NASA-related imaging projects, highlighting an ability to span firmware to silicon. Based in Burlington, MA, he blends rigorous EE/CS training with pragmatic delivery in production CPU design, and he often brings cross-domain insights from embedded verification and photonics test automation into microarchitectural problem solving.
8 years of coding experience
5 years of employment as a software developer
Bachelor's degree Electrical and Electronics Engineering Computer Science, Bachelor's degree Electrical and Electronics Engineering Computer Science at Rochester Institute of TechnologyTulsa Technology Center-Lemley Campus
Github Skills (4)
testing3
programming-language1
compiler1
interpreter1
Programming languages (2)
Github contributions (5)
Reed-Terdal/Programming-Language-Concepts-F2019
Sep 2019 - Dec 2019
Repository for Programming Language Concepts and the Jott Interpreter
Contributions:12 PRs, 17 pushes, 21 branches in 2 months
compilerprogramming-languageinterpreterprogramming-language-concepts
RIT-Landsat-Field-Radiometers/Specifications-and-Standards
Nov 2020 - May 2022
Contributions:1 push, 1 branch in 1 year 6 months
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