Reoma Matsuo
Software Architect at TIER IV, Inc.
Tokyo, Japan
Summary
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RockstarReoma Matsuo is a Software Architect and processor architect based in Tokyo with seven years of experience designing and verifying complex embedded systems. She has hands-on expertise in RISC-V out-of-order superscalar processor development, focusing on hardware implementation, post-synthesis simulation, and system-level tooling. Her open-source work on the rsd RISC-V project highlights practical skills in Block RAM configuration, dynamic submodule generation, and fixing environment and Makefile issues to ensure correct Vivado simulations. Comfortable across hardware and software boundaries, she brings a systems-thinking approach that reduces integration friction between RTL, build scripts, and verification flows. Colleagues rely on her to translate low-level design constraints into robust development practices that accelerate delivery. Her Tokyo base and processor-focused GitHub profile suggest strong alignment with both academic-quality design and production-ready engineering.
7 years of coding experience
Github Skills (14)
hardware-designs10
risc-v10
embedded10
vivado10
digital-design10
systemverilog10
sys10
digital-logic10
logic10
architecture9
architectures9
system9
verilog9
makefile8
Programming languages (3)
Github contributions (5)
rsd-devel/rsd
Dec 2019 - Aug 2022
RSD: RISC-V Out-of-Order Superscalar Processor
Role in this project:
Embedded Systems Engineer / System Architect
Embedded Systems Engineer / System ArchitectContributions:87 commits, 25 PRs, 68 pushes in 2 years 8 months
Contributions summary:Reoma primarily focused on modifying and improving the RSD processor's hardware implementation. They addressed bugs related to the environment setup and test program copying. A significant portion of their work involved modifying Block RAM configurations, including dynamic submodule generation and fixing issues for correct post-synthesis simulation in Vivado, showcasing their expertise in hardware design and verification. Furthermore, they made changes to the Makefile and related scripts for correctly running and verifying the post-synthesis simulation, which is a good indicator of their system-level expertise.
risc-vasicout-of-orderriscsuperscalar
reo-pon/reo-pon.github.io
Apr 2019 - Apr 2020
Contributions:5 pushes, 1 branch in 1 year
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