Riccardo Tedeschi
PhD Candidate
Summary
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RockstarRiccardo Tedeschi is a PhD candidate with six years of hands-on experience in embedded systems and RISC-V CPU design. He contributes to the well-known open-source CORE-V CVA6 project, focusing on cache subsystem improvements, performance counter fixes, and adding a branch predictor with private history. His work spans SystemVerilog modifications, low-level register and FIFO control, and resolving complex compilation and parameterization issues—skills that bridge research and production-grade hardware. While academically oriented, Riccardo demonstrates practical impact by enabling Linux-bootable CPU features and improving microarchitectural reliability. He combines deep hardware design expertise with a collaborative open-source mindset, making him effective at turning architectural ideas into verifiable implementations.
6 years of coding experience
Github Skills (5)
fpga10
cpu10
risc-v10
asic10
systemverilog-hdl10
Programming languages (9)
Github contributions (5)
openhwgroup/cva6
Aug 2024 - Mar 2025
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:4 reviews, 8 PRs, 13 comments in 6 months
Contributions summary:Riccardo's contributions focus on hardware-related aspects of the CVA6 RISC-V CPU, including cache subsystem enhancements and performance counter fixes. They implemented an AW lock register to manage the W FIFO push signal, which required modifications to SystemVerilog code. Additionally, the user addressed compilation errors by initializing signals and corrected parameter issues related to the HPDcache, demonstrating their expertise in the hardware design and configuration of the CPU. They also added a branch predictor with private history.
cpurisc-vasicbootingariane
pulp-platform/ace
Apr 2024 - Mar 2025
Contributions:8 PRs, 33 pushes, 20 branches in 10 months
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