Richard Herveille
Nios V Solutions Architect at Altera
Folsom, California, United States
Summary
👤
Senior🎓
Top SchoolRichard Herveille is a principal engineer and FPGA/ASIC architect with 30+ years of hands-on experience designing RTL, verification, synthesis and system-level architectures, and over 20 years focused on programmable logic and SoC design. He currently leads Nios V architecture efforts at Altera while running Roa Logic, where he develops IP and a RV12 RISC-V CPU-based SoC, blending product strategy with technical sales and EDA support. His background spans senior engineering, field applications, and management roles at Intel, eASIC and Flextronics, giving him a rare combination of deep implementation skill and customer-facing systems expertise. Proficient across Verilog/SystemVerilog/VHDL, Cadence and vendor toolflows, he’s also experienced in high-speed memory/serial interfaces, video IP, and secure device lifecycle management. Based in Folsom, CA, he pairs academic study in computer architecture with practical IP development and a history of enabling first-time-right customer designs. An owner and main contributor of RoaLogic, he brings both entrepreneurial initiative and established semiconductor domain leadership.
10 years of coding experience
21 years of employment as a software developer
Computer Architecture, Computer Architecture at Princeton UniversitySintermeerten CollegeBSEE Digital/Electrical Engineering Computer Sciences, BSEE Digital/Electrical Engineering Computer Sciences at Heerlen PolytechnicsMSc Advanced MicroElectronics, MSc Advanced MicroElectronics at The University of BoltonBSEE Electronics / Computer Sciences, BSEE Electronics / Computer Sciences at Zuyd Hogeschool | Zuyd University of Applied Sciences
Dutch, limburgish, English, Thai, German
Github Skills (37)
switch10
synthesis10
cpu10
risc-v10
yosys10
amba10
risc10
computer-engineering10
sketchup10
devkit9
debug9
jtag9
python9
timer9
interrupt9
Programming languages (4)
Github contributions (5)
RoaLogic/riscv_gnu_eclipse
Apr 2016 - Jun 2017
Contributions:29 commits, 18 pushes, 1 branch in 1 year 2 months
RoaLogic/ahb3lite_memory
Mar 2017 - Nov 2021
Multi-Technology RAM with AHB3Lite interface
Contributions:19 commits, 2 PRs, 18 pushes in 4 years 8 months
adaramdubdatabase-accesshal
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