Ricky Dua
ASIC Design Engineer at Cornelis Networks
Sydney, New South Wales, United States
Summary
👤
Senior🎓
Top SchoolRicky Dua is an ASIC Design Engineer with 11 years of experience in digital logic, physical design, and analog design methodology, currently driving ASIC work at Cornelis Networks after a decade-long tenure at Intel. He is proficient in RTL (Verilog/VHDL), synthesis, STA, layout and verification, and well-versed with Synopsys/Cadence toolflows, Hspice, Modelsim/VCS and test tools like Tetramax. Ricky’s background spans component-to-chip-level roles—from test-chip hardware and yield analysis at AMD to physical and analog methodology engineering at Intel—giving him a practical understanding of silicon bring-up and production reliability. Based in Sydney, he combines hands-on circuit simulation and scripting (MATLAB, C/C++, UNIX) with a systems view of performance testing and problem solving. An understated strength is his cross-domain fluency bridging analog/physical constraints with RTL design choices to accelerate tapeout closure.
11 years of coding experience
14 years of employment as a software developer
MS Electrical Engineering, MS Electrical Engineering at The University of Texas at DallasB.S Electrical Engineering, B.S Electrical Engineering at SRM University
Github Skills (19)
python10
kubernetes9
django9
orm8
face-recognition4
face-detection3
computer-vision3
web-framework3
object-detection3
debian-based3
aws-lambda3
aws-lambda-layer3
unattended-upgrades2
frontend2
opentelemetry2
Programming languages (5)
Github contributions (5)
rickydua/homelab-ansible
Jan 2022 - Oct 2022
Contributions:25 commits, 16 pushes in 8 months
rickx34/docker-compose
Jul 2019 - Feb 2021
Contributions:3 pushes, 1 branch in 1 year 7 months
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