Rinse Wester
Senior HW Designer at Ponos Technology
Greater Enschede Area Netherlands
Summary
👤
Senior🎓
Top SchoolRinse Wester is a Senior HW Designer and freelance FPGA/software consultant with a decade of experience building high-throughput digital signal processing and multi-gigabit transceiver systems for medical, communications and industrial applications. As founder of Westpulse and current senior designer at Ponos Technology, he combines hands-on RTL/IP development, verification (SystemVerilog, cocotb), and hardware-in-the-loop CI workflows to deliver end-to-end FPGA solutions and embedded software interfaces. His background includes FPGA work on RFNoC platforms, DAQ and image-processing systems, and audio IP, reflecting a strong practical bridge between research (PhD/postdoc) and product-grade engineering. Colleagues know him for tackling STA/CDC challenges and bringing DSP expertise to complex real-time designs while steering projects from IP to full system verification.
9 years of coding experience
7 years of employment as a software developer
Master of Science (M.Sc.), Computer Science, Master of Science (M.Sc.), Computer Science at University of Twente
Github Skills (7)
sdf8
synchronous8
simulation7
code-generation6
drawing2
python2
visualization1
Github contributions (2)
rinsewester/SDFkit
Jun 2016 - Feb 2019
Contributions:1 release, 228 commits, 3 PRs in 2 years 8 months
code-generationsdfsimulationgraphsdata-flow
rinsewester/SchemaViz
Sep 2017 - Mar 2018
Contributions:4 PRs, 22 pushes, 5 branches in 5 months
pythondrawing-librarydrawingvisualization
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