Rishiyur Nikhil
CTO at Bluespec, Inc
Arlington, Massachusetts, United States
Summary
🤩
Rockstar🎓
Top SchoolRishiyur Nikhil is a seasoned CTO and hardware design expert with over a decade of experience leading Bluespec, Inc.’s technical strategy and product direction for RISC-V-focused CPU and SoC verification tools. He combines deep formal-methods knowledge and hands-on hardware modeling—particularly in RISC-V and Bluespec SystemVerilog—with active contributions to the Sail RISC-V model implementing double-precision floating-point semantics. A long-time participant and chair in RISC-V Foundation technical groups (including ISA Formal Semantics), he shapes standards around verification, memory models, debug and security. Based in Arlington, MA, he bridges research-grade formal specification work (Haskell, RISC-V formal specs) with practical IP and tool delivery for industry. Notably, his open-source work extends formal and executable models that improve confidence in floating-point and ISA behavior across implementations.
11 years of coding experience
Indian Institute of Technology KanpurPh.D., Ph.D. at University of Pennsylvania
Github Skills (11)
risc-v10
floating-point10
float3210
architectures10
architecture10
computer-architecture10
instruction-set10
modeling9
model-driven9
model-building9
modeler9
Programming languages (15)
Github contributions (5)
riscv/sail-riscv
Sep 2019 - Oct 2019
Sail RISC-V model
Role in this project:
Back-end Developer
Back-end DeveloperContributions:79 reviews, 11 commits, 3 PRs in 1 month
Contributions summary:Rishiyur implemented features for the F and D floating-point extensions within the Sail RISC-V model. Their work included adding new files for instruction specifications, defining rounding modes, and implementing execution semantics for floating-point load/store and fused multiply-add instructions. The user completed execute clauses for arithmetic operations and conversion functions. These changes contribute to expanding the model's capabilities to accurately simulate double-precision floating-point operations.
risc-v
rsnikhil/Forvis_RISCV-ISA-Spec
Jan 2018 - Mar 2020
Formal specification of RISC-V Instruction Set
Contributions:90 commits, 5 PRs, 73 pushes in 2 years 1 month
instruction-setrisc-v
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