Ritu Raj
Timing Design Engineer at Apple
Cupertino, California, United States
Summary
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Senior🎓
Top SchoolRitu Raj is a Timing Design Engineer with a decade of experience in SoC and ASIC physical design, currently shaping timing closure at Apple after roles at AMD, NVIDIA, and Intel. She brings deep RTL-to-GDS flow expertise—synthesis, STA, SpyGlass linting, formal equivalence, and Calibre checks—paired with practical scripting skills in Perl and Verilog automation to speed up design flows. Her background includes hands-on 7nm and 14nm process work on 5G modem SoCs and a USC MS with coursework in advanced VLSI and computer architecture. Equally comfortable in front-end verification and back-end optimization, she blends analytical rigor with clear communication to drive cross-functional integration. A data-curious engineer who also explores machine learning tooling, she bridges hardware precision with a penchant for data-driven efficiency improvements.
10 years of coding experience
5 years of employment as a software developer
Master of Science - MS Computer Engineering, Master of Science - MS Computer Engineering at University of Southern CaliforniaBachelor of Technology (BTech) Electrical Electronics and Communications Engineering, Bachelor of Technology (BTech) Electrical Electronics and Communications Engineering at Manipal Institute of TechnologyCBSE 12th Mathematics and Computer Science, CBSE 12th Mathematics and Computer Science at ST. MICHAEL'S HIGH SCHOOLProgramming languages (2)
Github contributions (5)
strar-buck/ML_ques_ans
Feb 2017 - Feb 2017
Contributions:7 commits, 1 push, 1 branch in 1 day
djangoconfire/django_sport_app
Apr 2017 - Apr 2017
Contributions:27 pushes, 1 branch in 1 day
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