Summary
Ritvik Krishnamurthy is a Staff Engineer with 10 years of experience specializing in microarchitecture, RTL design, and verification for high-performance storage and GPU SoCs, with deep expertise in SAS/SATA PHY layers, DMA, RAID engines and multi-clock-domain designs. He has driven multiple tape-outs from specification through RTL, synthesis and timing closure, and led cross-functional verification and bring-up efforts that resolved complex digital PHY/serdes/firmware interoperability issues. Comfortable at both module and chip top-level verification, he builds constrained-random testbenches, scoreboards and verification plans, and has hands-on experience with Synopsys DesignWare, AXI/SAS VIPs and emulation workflows. Early FPGA work includes ADC controllers, PWM and fault diagnostics for automotive power electronics, reflecting a practical hardware-software integration mindset. Based in San Jose and holding an M.S. in Computer Engineering from IIT, he maintains a public work sample repository that highlights applied RTL and verification artifacts. Notably, he combines formal standards-driven design translation with a knack for rooting out subtle cross-domain timing and interoperability failures during silicon bring-up.
10 years of coding experience
10 years of employment as a software developer
Bachelor's Degree, Electronics & Communications, Bachelor's Degree, Electronics & Communications at National Institute of Engineering, Mysore, India
Master's Degree, Computer Engineering, 3.8 / 4, Master's Degree, Computer Engineering, 3.8 / 4 at Illinois Institute of Technology
English