Robert Balas
PHD Student at ETH Zürich
Zurich, Zurich, Switzerland
Summary
🤩
Rockstar🎓
Top SchoolRobert Balas is a Zurich-based PhD student and embedded systems engineer with a decade of experience in low-level hardware verification, test automation, and RISC-V CPU development. At ETH Zürich he focuses on integrated systems, contributing practical improvements to verification flows and JTAG/debug tooling while pursuing advanced research. His open-source work on notable projects like the CV32E40P core and PULPissimo shows hands-on expertise in Verilator modeling, PMP support, single-stepping, and OpenOCD integration—skills that bridge silicon behavior and system-level debugging. Colleagues value his attention to hard-to-reproduce hardware issues and his knack for making simulation and debug environments more robust and configurable. He brings a solid academic foundation in electrical engineering from ETH Zürich combined with military discipline gained during Swiss service.
10 years of coding experience
Bachelor's degree, Elektrotechnik und Informationstechnologie, Bachelor's degree, Elektrotechnik und Informationstechnologie at ETH Zürich
German, English, French
Github Skills (15)
risc-v10
verilog10
embedded10
jtag10
systemverilog10
sys10
test-automation10
hardware9
signal-processing9
digital-signal-processing9
hardwareid9
verification9
formal-verification9
verilator8
openocd8
Programming languages (19)
Github contributions (5)
pulp-platform/pulpissimo
Jun 2018 - Nov 2022
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
Role in this project:
Embedded Systems Engineer / Test Automation Engineer
Embedded Systems Engineer / Test Automation EngineerContributions:1 release, 30 reviews, 371 commits in 4 years 5 months
Contributions summary:Robert primarily contributed to the testbench and debugging tools within the PULPissimo platform. Their work involved implementing and refining JTAG-related test tasks and functionalities. Specific changes included adding new debug unit tests, improving the srec loading process, fixing indexing issues, and enhancing the simulation environment to include configurable boot modes and openocd integration. This involved significant interaction with system-level debugging, JTAG interface, and test automation, suggesting a focus on hardware verification and low-level system interaction.
pulpcpusocdomainelectrical-engineering
openhwgroup/cv32e40p
Jul 2018 - Mar 2022
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Role in this project:Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:4 reviews, 196 commits, 61 PRs in 3 years 8 months
Contributions summary:Robert primarily contributed to the verification and enhancement of the CV32E40P, an in-order RISC-V CPU. They made several modifications to the Verilator model, including fixing compilation issues, adding PMP support, and addressing assignments that Verilator couldn't handle. Further, the user added functionality for single-stepping, and addressed breakpoint behavior, demonstrating a focus on low-level hardware debugging and verification.
risc-vcpupulpuvmriscv
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.