Robert Ursua
NAND Array Engineer at Solidigm
San Francisco Bay Area United States
Summary
👤
Senior🎓
Top SchoolRobert Ursua is a NAND array engineer with a decade of experience designing, characterizing, and improving TLC/QLC NAND devices across leading memory companies including Micron, Intel, SK hynix, and Solidigm. He combines deep device-physics expertise with practical skills in bench experiment design, firmware/REM edits, silicon micro-probing, and automation scripting (Python/Perl/JSL) to translate root-cause insights into waveform and trim mitigations that raise yield and reliability. At Micron and Intel he drove cross-functional alignment between product, test, probe, and qual teams to deliver next‑gen NAND improvements and uncover corner-case failure modes through improved test pattern randomization. Known for bridging first-principles modeling with hands-on test execution, he also builds bespoke test automation (including Raspberry Pi-based rigs) to accelerate data collection and DOE validation. Based in the San Francisco Bay Area, he pairs strong academic foundations from UCLA with a knack for pragmatic prototyping that shortens time-to-silicon.
10 years of coding experience
6 years of employment as a software developer
High School, High School at Philippine Science High School - Main CampusEngineering, 4.00/4.00, Engineering, 4.00/4.00 at City College of San FranciscoBachelor’s Degree, Electrical Engineering, 3.75/4.00, Bachelor’s Degree, Electrical Engineering, 3.75/4.00 at University of California, Los AngelesStudied Electrical, Electronics and Communications Engineering, 3.60/4.00, Studied Electrical, Electronics and Communications Engineering, 3.60/4.00 at University of the Philippines
English, TagalogProgramming languages (1)
Github contributions (5)
dailybruin/BruinWalkChromeExtension
Dec 2016 - Nov 2019
Contributions:15 PRs, 23 pushes, 11 branches in 2 years 11 months
preethamrn/BruinWalkChromeExtension
Dec 2016 - Dec 2016
Contributions:21 commits in 4 days
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