Rodrigo聽Melo
Technical Director, Digital Design & FPGA at indie.inc
Buenos Aires, Argentina
Summary
馃懁
Senior馃帗
Top SchoolRodrigo Melo is a Technical Director and digital electronics engineer with 13+ years designing SoCs, NoCs and FPGA prototypes for ADAS, LiDAR, radar and vision systems. He pairs hands-on RTL expertise in Verilog/SystemVerilog and VHDL with vendor-independent FPGA experience across the four major manufacturers and a long history of GNU/Linux and free-software toolchain advocacy. Rodrigo has led top-level integration and high-speed transceiver projects, developed IP cores (USB, Ethernet, HDMI, FFT) and taught FPGA courses at ICTP, showing both production and academic chops. As an active contributor to the Yosys open synthesis suite, he improved Verilog frontend handling and added robust tests鈥攗nderscoring his commitment to open toolchains. He brings practical systems engineering from board bring-up and bootloader debugging to web-enabled embedded interfaces, plus experience delivering consulting solutions in hardware acceleration and ML. Based in Buenos Aires, he combines deep low-level design skills with a pragmatic, vendor-neutral approach to long-term, testable hardware-software systems.
13 years of coding experience
19 years of employment as a software developer
T茅cnico Electr贸nico, T茅cnico Electr贸nico at EET N掳8Ingeniero Electr贸nico Ingenier铆a electr贸nica, Ingeniero Electr贸nico Ingenier铆a electr贸nica at UTN - Facultad Regional Haedo
Spanish, English
Stackoverflow
1reputation
26reached
0answers
1question
Github Skills (9)
yosys10
verilog10
front-end-development10
testing9
c-language8
cprogramming-language8
digital-design8
open-source7
svn6
Programming languages (13)
Github contributions (5)
YosysHQ/yosys
Dec 2019 - Feb 2020
Yosys Open SYnthesis Suite
Role in this project:
Back-end Developer
Back-end DeveloperContributions:14 commits, 2 PRs, 44 comments in 1 month
Contributions summary:Rodrigo primarily focused on enhancing the Verilog frontend of the Yosys Open SYnthesis Suite, addressing issues related to memory content file inclusion using `$readmem[hb]`. Their contributions involved improving the handling of relative file paths, correcting bugs, and adding comprehensive tests to ensure functionality across various scenarios. Furthermore, the user standardized code by replacing `strlen` with `GetSize` and solved a conflict in the CHANGELOG file.
synthesispythonsuiteyosys
PyFPGA/pyfpga
Oct 2019 - May 2022
A Python package to use FPGA development tools programmatically.
Contributions:9 reviews, 510 commits, 38 PRs in 2 years 7 months
amdpythonvivadoxilinxlattice
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