Summary
Rohan Garg is a Performance Architect with 16 years of experience specializing in SoC architecture and memory subsystem performance for client processors, currently shaping memory controller and encryption IP performance at Intel since 2017. He has delivered end-to-end performance evaluations and C++-based models across multiple client SoC generations (Alder Lake onward) and an industry SoC, combining architecture feature definition with RTL and post-silicon correlation. An electronics engineer by training from BITS Pilani Goa, he brings deep DRAM controller, DRAM technology and security-IP expertise and hands-on modeling for performance enhancements. Outside silicon, he contributes to open-source—helping improve the widely used Calamares installer and active in the Mesa3D ecosystem—demonstrating a practical full-stack mindset that spans low-level modeling to user-facing tooling.
16 years of coding experience
14 years of employment as a software developer
Executive MBA, Business Administration and Management, General, Executive MBA, Business Administration and Management, General at University of California, Berkeley
Executive MBA, Leadership Award recipient, Business Administration and Management, General, Executive MBA, Leadership Award recipient, Business Administration and Management, General at Esade
Executive MBA, Business Administration and Management, General, Executive MBA, Business Administration and Management, General at American University in Dubai
Executive MBA, Business Administration and Management, General, Executive MBA, Business Administration and Management, General at GLOBIS University - Graduate School of Management
Bachelor Of Technology, ECE, Bachelor Of Technology, ECE at ITM University
Executive MBA, Business Administration and Management, General, Executive MBA, Business Administration and Management, General at Imperial Business School