Summary
Ryan Forelli is a PhD student in computer engineering at Northwestern with six years of hands-on experience delivering ultra-low-latency machine learning on FPGAs for real-time imaging, control, and scientific instrumentation. He has repeatedly beaten GPU latencies—demonstrating microsecond-scale inference (as low as 7.7µs and 14µs) by co-designing CNNs, HLS implementations, and firmware for frame grabber and accelerator platforms. His work spans applied research and product-focused engineering, from accelerating cancer immunotherapy cell sorting and neuroscience interventions to enabling real-time feedback control for Tokamak fusion experiments. Ryan pairs strong hardware design skills (Verilog, HLS, Vivado timing closure) with practical systems integration (LabVIEW, AXI-stream, PCIe) and a knack for tooling and tutorials that lower the barrier for deploying ML on FPGAs. Unusually for an academic, he has driven industry-collaborative, reproducible deployments and public-facing tutorials that make high-speed on-device inference accessible.
6 years of coding experience
3 years of employment as a software developer
High School Diploma, High School Diploma at Honesdale High School
Doctor of Philosophy - PhD, Computer Engineering, Doctor of Philosophy - PhD, Computer Engineering at Northwestern University
Bachelor of Science - BS, Computer Engineering, Bachelor of Science - BS, Computer Engineering at Lehigh University