Ryota Shioya
准教授 at 東京大学
Japan
Summary
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RockstarRyota Shioya is an associate professor at the University of Tokyo and Nagoya University with 11 years of experience at the intersection of academia and systems engineering. His work centers on processor design and automation, evidenced by contributions to an open-source RISC-V out-of-order superscalar processor where he streamlined build and Vivado simulation workflows. He combines research-grade rigor with practical tooling improvements, often focusing on build reliability and test automation that accelerate hardware-software co-design. Based in Japan, he brings a blend of teaching, research leadership, and hands-on back-end development to projects that bridge lab prototypes and reproducible engineering. An attention to development environment robustness hints at a preference for enabling teams and students to move from concept to validated implementation efficiently.
10 years of coding experience
Github Skills (6)
risc-v10
verilog10
systemverilog10
build-automation9
bash9
makefile8
Programming languages (7)
Github contributions (5)
rsd-devel/rsd
Dec 2019 - Sep 2022
RSD: RISC-V Out-of-Order Superscalar Processor
Role in this project:
Back-end Developer & Automation Engineer
Back-end Developer & Automation EngineerContributions:1 release, 149 commits, 32 PRs in 2 years 9 months
Contributions summary:Ryota's contributions primarily involved modifying build scripts and configuration files, indicating a focus on streamlining the development process. They made changes to a batch file related to environment variable settings, likely for build tools. Additionally, the user integrated support for Vivado simulation by adding necessary files and configurations to the project. This suggests a role in both back-end development of the processor and automation of its build and test processes.
risc-vasicout-of-orderriscsuperscalar
shioya-lab/how-to
Aug 2022 - Feb 2023
Contributions:28 commits, 29 pushes, 1 branch in 5 months
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