Sagar Karandikar
Assistant Professor Of Electrical Engineering And Computer Sciences (EECS) at University of California, Berkeley
Berkeley, California, United States
Summary
🤩
Rockstar🎓
Top SchoolSagar Karandikar is an Assistant Professor of EECS at UC Berkeley and Jean and Hing Wong Foundation Faculty Fellow who specializes in hardware/software co-design for hyperscale cloud data centers powering AI/ML and large-scale web services. His group at the SLICE Lab develops open-source, full-stack accelerator and SoC tooling—most notably FireSim and Chipyard—that have been adopted across academia, industry, and DARPA/IARPA programs. He blends deep systems research with production-focused engineering, having integrated and automated complex build and toolchain workflows (e.g., RISC-V QEMU and Chipyard build systems) to enable reproducible, agile hardware development. His work has earned multiple artifact and retrospective honors and the 2025 ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award for practical impact at hyperscalers. With a Ph.D., M.S., and B.S. from UC Berkeley plus years of collaboration at Google, he combines rigorous academic training with hands-on experience shipping tools used in commercial chip development. An often overlooked strength is his emphasis on developer ergonomics and reproducible build automation, which has materially increased community adoption of his platforms.
14 years of coding experience
10 years of employment as a software developer
Doctor of Philosophy (Ph.D.), Computer Science, Doctor of Philosophy (Ph.D.), Computer Science at University of California, Berkeley
Github Skills (14)
risc-v10
git10
sh10
script10
bash10
shell10
scripting10
build-automation10
qemu10
cicd10
git-submodules9
automation9
automations9
management9
Programming languages (11)
Github contributions (5)
riscv-software-src/riscv-tools
Jul 2014 - Feb 2016
RISC-V Tools (ISA Simulator and Tests)
Role in this project:
Automation Engineer / Build & Release Engineer
Automation Engineer / Build & Release EngineerContributions:22 commits, 2 PRs, 4 pushes in 1 year 6 months
Contributions summary:Sagar primarily focused on integrating and managing the riscv-qemu component within the riscv-tools repository. Their work involved adding, removing, and building the qemu component using build scripts. They also addressed submodule references and potentially managed build dependencies and version upgrades, demonstrating their skills in build system management and toolchain integration.
risc-visariscvsimulatorrisc
ucb-bar/chipyard
Sep 2019 - Oct 2022
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Role in this project:Automation Engineer / Build & Release Engineer
Automation Engineer / Build & Release EngineerContributions:3 releases, 39 reviews, 118 commits in 3 years 1 month
Contributions summary:Sagar primarily focused on build and release automation within the Chipyard project. Their contributions include modifying build scripts, setting up environment variables, and streamlining the build process for toolchains and dependencies. The user's work also involved fixing issues related to open file limits and improving the setup scripts for the FireSim environment. Additionally, they updated the submodule management and configuration files to ensure build reproducibility and proper submodule initialization.
rtlout-of-orderhardware-designsvlsicomputer-engineering
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