Sahand Kashani is a system architect with 12 years of experience bridging academia and industry, currently designing DPU subsystems (PCIe, storage, etc.) at MangoBoost in Seoul. He holds a PhD in Computer Science from EPFL and spent a decade there teaching and researching computer architecture, reconfigurable systems, and hardware accelerators. His background spans hands-on FPGA and SoC work—from partial reconfiguration platforms and SoC-FPGA integration to a Microsoft internship building a control processor for BrainWave—giving him deep systems-level insight. An active contributor to the Yosys open-source synthesis suite, he enhanced its Firrtl backend to improve file metadata and blackbox handling, reflecting a knack for practical tooling that aids hardware design flows. Colleagues rely on him for combining compiler and architecture thinking to deliver scalable, reconfigurable accelerator solutions.
12 years of coding experience
Master’s Degree, Computer Science (Specialization in Computer Engineering), Master’s Degree, Computer Science (Specialization in Computer Engineering) at Ecole polytechnique fédérale de Lausanne
Doctor of Philosophy - PhD, Computer Science, Doctor of Philosophy - PhD, Computer Science at EPFL (École polytechnique fédérale de Lausanne)
Contributions:19 commits, 8 PRs, 26 comments in 8 months
Contributions summary:Sahand primarily focused on enhancing the Firrtl backend of the Yosys Open SYnthesis Suite. Their contributions involved adding file information to various components such as the top-level circuit, modules, wires, instances, assignments, and non-instance cells. They also refactored the code to handle file information emission and added support for blackbox components including the generation of parameters.
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