Sai Chalamalasetti
AI Systems Architect at d-Matrix
Pleasanton, California, United States
Summary
👤
Senior🎓
Top SchoolSai Chalamalasetti is an AI Systems Architect and systems researcher with a decade of server system architecture experience and over 14 years designing and prototyping on AMD and Intel FPGAs. He blends hardware-software co-design, RTL development (Verilog/VHDL/SystemVerilog), and lab-level debug to deliver CXL, PCIe, high-speed transceiver and memory-controller proofs-of-concept for data-center architectures. His work spans concept-to-tapeout for silicon photonics and memristor-based accelerators, and he has led multi-engineer teams building multi-Gbps FPGA platforms and 100+ node system architectures. Based in Pleasanton, CA, Sai has deep simulation expertise with Cadence and Synopsys tools and a history of integrating novel fabrics like Gen-Z and CXL into real server platforms. Notably, he bridges research and production by mapping high-level algorithms into FPGA APIs and has repeatedly translated academic projects into industry tapeouts and demos.
8 years of coding experience
15 years of employment as a software developer
UMass LowellHigh School, High School at Sree Sree Educational SocietyBachelor of Technology Electronics and Computer Engineering, Bachelor of Technology Electronics and Computer Engineering at Koneru Lakshmaiah College of Engineering (KLCE)
English, Telugu, Hindi
Github Skills (12)
cache-control8
pluggable6
compile-time6
concurrency5
cpp5
lru5
memory-allocation5
caching5
scale4
in-memory4
redis4
high-performance3
Programming languages (1)
Github contributions (2)
Aayush-Ankit/ml-inference-benchmarks
Nov 2017 - Nov 2017
Contributions:20 commits in 12 days
facebook/CacheLib
Jun 2024 - Jul 2024
Pluggable in-process caching engine to build and scale high performance services
Contributions:2 comments, 2 issues in 28 days
lrucache-controlpluggablecompile-timecache-engine
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