Sai Ilapakurthi is a hardware engineer with 9 years of experience designing and optimizing RTL for machine learning accelerators, currently contributing to ML hardware at Google after prior roles at Microsoft and Samsung. He combines hands-on Verilog and EDA tool expertise with scripting (Shell, Perl) to drive microarchitecture, timing optimization, and PPA improvements across NPUs and DL accelerators. Sai’s background spans academic research and teaching at Purdue to industry work on FPGA-based ML inference and custom ALU/ASIP blocks, giving him a strong bridge between architecture and implementation. He’s pragmatic about tooling and automation—having built scripts and a prediction tool for area/power—and enjoys electronics hobby projects around microcontrollers and IoT that inform his hardware intuition. Based in San Jose, he focuses on SOC design, digital logic, and computer architecture, bringing both systems-level perspective and detailed RTL craftsmanship to high-performance ML hardware.
9 years of coding experience
4 years of employment as a software developer
Bachelor of Technology (B.Tech.) Electrical Electronics and Communications Engineering, Bachelor of Technology (B.Tech.) Electrical Electronics and Communications Engineering at National Institute of Technology, Tiruchirappalli
Master's degree Electrical and Computer Engineering , Master's degree Electrical and Computer Engineering at Purdue University
Contributions:7 PRs, 15 pushes, 3 branches in 9 months
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